(1) Field of the Invention
The present invention relates to a CMOS-type SRAM device and a method for fabricating the same, and more particularly to a fully CMOS-type SRAM device in which load transistors of a flip-flop memory cell are constructed by p-channel thin-film MOS transistors and a method for fabricating the same.
(2) Description of the Related Art
The memory cell structure of a fully CMOS-type SRAM device is disclosed in, e.g., "SINGAKU GIHO" Vol. 90, No. 48, pp. 7-13 (SDM90-25), JP-A-1-166554, and JP-A-1-202858. Its typical example will be explained with reference to FIGS. 1A, 1B and FIG. 2. FIGS. 1A and 1B are plan views of a fully CMOS-type SRAM which has as load elements bottom-gate type p-channel MOS thin film transistor (hereinafter simply referred to as "p-TFTs"). FIG. 2 is a sectional view taken along the line A--A in FIG. 1A.
This prior art SRAM has four thin film conductor layers and one Al (aluminum) interconnect wiring layer stacked on a semiconductor substrate. Specifically, these layers are, from the lowest layer, a gate electrode of a driver MOS transistor; a grounding (GND) wiring connected with the source of the driver MOS transistor; a bottom gate electrode of the p-TFT; a source, drain, channel of the p-TFT and a power supply line; and a bit line.
Hereunder, the structure of the above prior art SRAM device will be explained more specifically.
The driver MOS transistors of a flip-flop circuit are composed of an n.sup.+ -impurity-doped region (hereinafter referred to an impurity region) if serving as a common source, n.sup.+ -impurity regions 1e, 1d constituting drains, and gate electrodes 3b, 3c. The gate electrodes 3b and 3c are cross-connected, through contact holes 2b and 2c, with the impurity regions 1e and 1d, respectively, which serve as the drains of paired transistors for each other.
The n-channel transfer MOS transistors connected with the flip-flop are composed of n.sup.+ -impurity regions 1c, 1e serving as sources, n.sup.+ -impurity regions 1a, 1b serving as drains, and a common gate electrode 3a serving as a word line. The impurity region 1d also constitutes the drain of the driver MOS transistor. The impurity region 1c is connected with the n.sup.+ -impurity region 1e constituting tile drain of the driver transistor through the contact holes 2a, 2c and the gate electrode 3b. These impurity regions 1e, 1d and the gate electrodes and impurity regions connected with them constitute storage nodes.
The above n.sup.+ -impurity regions 1a and 1b are connected with bit lines 17a and 17b which are Al interconnect wirings through contact holes 16a and 16b, respectively. The n.sup.+ -impurity region 1f constituting the common source of the driver MOS transistors is connected, through a contact hole 4, with a grounding (GND) wiring layer which is formed by the second layer wiring.
The load elements which are bottom gate type TFTs are composed of gate electrodes 7a and 7b which are connected with the gate electrodes 3b and 3c of the driver MOS transistors through the contact holes 6a' and 6b', respectively, and semiconductor thin films 9a and 9b which are formed on them through a gate insulating film 8.
The semiconductor thin films 9a and 9b form drain regions 10a, 10b, source regions 12a, 12b, channel regions 14a, 14b and offset regions 15a, 15b of the TFTs, and also form power supply wiring layers 13a, 13b for supplying power to the memory cell.
The drain regions 10a and 10b of the TFTs are connected with the gate electrodes 7a and 7b through contact holes 11a and 11b, respectively, and constitute storage nodes together with the gate electrodes 7a and 7b, the gate electrodes 3b and 3c of the driver MOS transistors and the impurity regions 1c through 1d. The source regions 12a and 12b of the TFTs are connected with the power supply wiring layers 13a and 13b, respectively. Further, in order to improve the cut-off characteristics of the TFT, i.e., to reduce the off currents, the offset regions 15a and 15b doped with no impurity are provided between the channel regions 14a, 14b and the drain regions 10a, 10b, respectively.
The prior art described above has the following problem to be solved. In order to ensure or enhance the stability of the CMOS-type SRAM cell, it is important to supply the grounding potential to a flip-flop with a low Impedance. Where it is attempted to realize a minute cell size, the conventional cell structure cannot permit a large width of the grounding wiring layer 5 because of the limitation of layout, which makes it difficult to provide the grounding line with a low impedance. Namely, in the conventional cell structure, the width of the grounding wiring layer is determined by the positions of the contact holes 6a' and 6b' between which a margin should be left. Therefore, the width of the grounding wiring layer cannot be enlarged.
It is known that the off current of the load TFT is greatly affected by the electric field strength at the drain edge of the TFT. However, the conventional cell structure has the following structural problems. Namely, in the conventional cell structure, the gate electrodes 3b and 3c of the driver MOS transistors are located below the offset regions 15a and 15b of the TFTs. For this reason, the potential of the underlying gate electrode generates a change in the electric strength field for the drain of the TFT, which makes the off current characteristic unstable.
Further, in order to enhance the .alpha.-ray resistance characteristic of a memory cell, it is necessary to provide a storage node with sufficient capacitance. In the conventional cell structure, however, the capacitance of the storage node with respect to the grounding wiring layer cannot be made large because of the above limitation in the layout of the grounding wiring layer. These are problems to be solved by the invention, in the conventional cell structure.